The present invention is generally directed to a measuring method and a measuring device for data communications networks which use asynchronous transfer mode (ATM).
ATM transfer systems are known, which are used to transmit synchronous digital signal strings, existing, for example, as digitized voice, digitized music, digitized images, or as a binary series of numbers, that have been split up into eight-bit-width data words and combined into packets; data packets of this kind are the payload of ATM cells. The AAL 1 format (ATM Adaptation Layer 1) is a customary cell format for transmitting synchronous data over ATM systems at a constant bit rate (CBR=constant bit rate). An AAL1 cell has 53 data words of eight bit length, i.e. 53 octets or bytes, of which five data words form the cell header, and another data word is used for numbering the data packet. 47 data words thus remain for the payload of the cell.
On the transmitting side, synchronous digital data strings are able to be easily converted into ATM cells. Since it is the transmission system, nowadays predominantly a fiber optic system of the so-called xe2x80x9csynchronous digital hierarchyxe2x80x9d (SDH) including the most frequently occurring STM1-interface, which predefines the transmitting bit rate of 155.52 Mbit/s, quite a few data systems employing the most frequently used synchronous transmission rate of 2.048 Mbit/s are able to be inserted into such an ATM transmission system. The individual 2.048 Mbit/s systems are distinguished by their individual cell header contents and can be reassigned later to the correct receiver.
Given a less than fully utilized transmission capacity over a 155.52 Mbit/s transmission route, it is possible to insert about 72 ATM cells of other users or idle cells into the gaps between two 2.048 Mbit/s payload cells of one specific data stream. Splitting the synchronous data stream into eight-bit words, as required in ATM cell formation, reduces the rate of the word clock or block clock in the processing and retransmission of signals at the parallel port to one eighth of 155.52 Mbit/s, resulting in 19.44 Mbit/s and facilitating the use of more highly integrated switch elements.
Greater difficulties have to be overcome on the receiving side to retrieve the original digital data string from the ATM cells of a specific data stream, because it is necessary to recover the synchronous data timing or clock. Clock recovery circuits require reference oscillators, whose frequency can be variably tuned within certain limits by the incoming line signal. VCOs (voltage controlled oscillators) are used to perform the variable tuning.
As long as the synchronous digital data strings continue to be transmitted at 2.048 Mbit/s, the receiver""s clock recovery circuit, equipped with an appropriate VCO, is properly set up for reconverting the incoming ATM cells. However, as soon as a lower or higher transmission rate is needed, for example in world-wide data communication traffic based on a customary, yet different, U.S. or Japanese standard, the variety of measuring methods is restricted by the availability of reference oscillators. Assuming it takes about eight weeks to acquire VCO modules to retrofit an ATM measuring instrument, a measurement could be delayed by this period of time, in the event of an urgently needed conversion.
An even greater problem is posed by payload measuring procedures when working with VBR data strings (VBR=variable bit rate), thus when the data that arise require a variable transmission rate. This is the case when working with MPEG encoded digitized television pictures, where the required transmission rate is a function of the changes in the differential-encoded picture content over time. Also the transmission of voice over ATM systems raises this measuring problem, because digitized voice transmission can occur with a transmission rate substantially lower than 2.048 Mbit/s.
Therefore, in the case of VBR data strings, the measuring procedure does well enough with ATM cell-oriented measuring methods; cell losses are registered using cell header data and mostly output as cell loss rates. However, ATM operating companies are obligated to transmit their customers""data and are asked about the quality of their networks with respect to these data. This customer data are inserted in the payload portion of the ATM cells. Therefore, a method for measuring the payload data is required, even when it is only a question of representing the time distribution of ATM cell losses in detail, cell for cell, to facilitate application of suitable error correction methods.
An object of the invention is to devise a measuring method and a measuring device for the asynchronous transfer mode used in telecommunications networks which functions without recovering the original synchronous data timing. This permits flexibility within the transmission rate of the synchronous customer data and that the measuring process also works with the variable bit rate of the original, synchronous digital data strings.
The present invention provides a measuring method for data communications networks which makes use of asynchronous transfer mode (ATM) for continuous payload measurements, particularly at a 19.44 Mbit/s parallel port of ATM transmission devices where ATM cells are applied. The cells in this case are composed of 53 eight-bit width data words, and whose 47 useful signal words (payload) originate from originally synchronous digital data strings, whose frequency (rate of occurrence) is determined by the bit rate of the originally synchronous digital data, and which permit the cell-by-cell reading out of the payload data. The payload data are fed consecutively and at a higher rate as burst data to a data test receiver, which is able to ascertain the correct or corrupted receipt of the transmitting-side data. The parallel data (DA0 through DA7) arrive together with a 19.44 Mbit/s block clock pulse (7) and a cell starting pulse (10) in an ATM cell evaluation circuit (2); in the evaluation circuit, the 47 payload words are extracted from the altogether 53 words of each valid ATM cell and are fed to data inputs (d0 through d7) of a memory (3). With the aid of a timed write signal (11), which is fed by the ATM cell evaluation circuit (2) to the memory input for the write signal (11), the 47 payload words are then read in one after another into the memory (3). The memory (3) indicates at which instant the cell contents are available and uses an empty flag signal (13) as a filling level indicator to start a clocked burst data generator (6), which is also timed by the block clock pulse (12). The generator uses the block clock pulse to produce different pulse bursts on separate lines (for example 14, 15, 16 and 19). With the aid of the first clock-pulse burst, the 47 payload words are read out one after another out of memory (3) and fed to the parallel inputs of a parallel-to-serial converter (4). This parallel-to-serial converter is supplied at its input (16) for shift/load signals with a specific number (in this case 47) of load pulses and, at its clock-pulse input (15), with clock pulses (in this case with eight times 47), which were produced as second and third pulse bursts. At a serial output (17), the parallel-to-serial converter relays, in the rhythm of the clock pulses, the payload data of an ATM cell to burst-data output (5), at a serial output (18) of the output (5).
Additional features or refinements of the present method include that the write signal (11) is clocked using the block clock pulse (7). The clocked burst data generator (6) is either likewise supplied with the block clock pulse (12) or, in an alternative embodiment, with a higher-rate block clock pulse via the clock-pulse supplier (20), with whose aid the clocked burst data generator (6) produces a specific number, in particular three different pulse bursts of the same duration. With the aid of the first clock-pulse burst, which is fed to the read-out control input (14) of the memory (3), the useful signal payload words (here 47) are read one after another via outputs (D0 through D7) out of the memory (3) and fed to the parallel inputs of the parallel-to-serial converter (4). In a manner suitable for the readout process, the parallel-to-serial converter (4) is supplied at its input (16) for the shift/load signals with corresponding load pulses (here 47) and, at its clock-pulse input (15), with a corresponding number (here with eight times 47) clock-pulses of the 19.44 Mbit/s clock pulse (12), which were produced as second and third pulse bursts by the clock-pulse burst generator (6). At its serial output (17), the parallel-to-serial converter (4) relays, in the rhythm of the clock-pulses, the payload data of an ATM cell to burst data output (5), and these data bursts and clock-pulse bursts (here 376 bit long) represent, ATM cell for ATM cell, consecutively, the originally synchronous transmitting measuring data, and are compared in the measuring receiver on a bit by bit basis to a synchronizable reference signal, and are continually supplied as a comparison result to the designated result protocol.
Another refinement includes that, to increase the clock-pulse of data being output to output (19), a higher-rate block clock-pulse supplier (20) is provided. The memory (3) indicates at its output (13) when cell contents are available, and starts clock-pulse burst generator (6), which works with the increased block clock-pulse of, for example, 42.0 Mbit per second, resulting in the generation of three different pulse bursts of the same duration, here, namely, a burst having 47 pulses in 5.25 Mbit/s rhythm on read line (14), a clock-pulse burst having eight-times 47 pulses in the 42.0 Mbit/s rhythm to input (15), and a pulse burst clocked in a 42.0 Mbit/s rhythm as load/shift signal to input (16) of the parallel-to-serial converter (4). The transmission rate within the output bursts may be increased from 19.44 to 42.0 Mbit/s; and only a time period of three idle cells may still be needed as a gap between the two valid ATM cells at the parallel port for switching on the ATM measuring tool (1), so that the originally synchronous transmitting-side transmission rate rises to maximally 35 Mbit/s. Alternatively, by using a fast-action switching circuit technique, such as ECL, for the parallel-to-serial converter (4), the clock-pulse burst generator (6), and the burst data output (5), one increases the transmission rate within the output burst from 19.44 to over 140 Mbit/s; then no gap exists between two valid ATM cells at the parallel port for switching on the ATM measuring tool (1), and as a result, the originally synchronous transmitting-side transmission rate rises to maximally 140 Mbit/s.
A still further refinement of the present method is that the measuring tool (1) is switched on at a point on the transmission route where the ATM data signals are available in 8-bit parallel, with a cell starting pulse signal (10), an 8-bit block clock pulse and, in some instances, with an idle cell identifier, or an identifier for the valid cells. At the output of the memory (3), the 8-bit data words are read out with one eighth of the block clock pulse and supplied to the parallel-to-serial converter (4), to be read out there serially using the block clock pulse. For each valid ATM cell, a data burst of the length of the number of payload bits contained therein and, matching this, a block clock-pulse synchronous clock-pulse burst of the same length is emitted by a clock output circuit (6). The synchronous data/clock bursts are supplied from the ATM measuring tool (1) to the data/clock-pulse inputs of a data measuring receiver.
The present invention also provides a measuring tool or device, in particular for implementing the present method, wherein parallel data (DA0 through DA7), a block clock pulse (7), a void cell identifier signal (8), and an identifier for valid cells (9) are switched to the input of an ATM cell evaluation circuit (2). The output of the ATM cell evaluation circuit (2) is linked to a memory (3) and via a block clock-pulse supplier (12) to a clock-pulse burst generator (6). Connected in outgoing circuit to memory (3) is a parallel-to-serial converter (4), which is timed and controlled (15 and 16) by clock-pulse burst generator (6) and which, in turn, is linked by its output (17) to a circuit of a burst-data output (5), at whose serial output (18) data are adapted to be tapped off for the data measuring receiver. Clock-pulse burst generator (6) receives an empty flag signal (13) from memory (3), and is linked to the input (16) of the serial-to-parallel converter (4) for the shift/load signal, as well as emits externally via the clock-pulse burst output (19) clock-pulse bursts matching the data, to the data measuring receiver.
Advantageous refinements include: (a) that to read the memory (3), the memory is linked to a clock-pulse (20) having a higher rate than the eighth clock pulse, enabling the time interval between two successive, valid ATM cells to be less than seven idle cells; (b) that the measuring tool is implemented using integrated circuit technology; (c) the measuring tool (1) is part of an ATM measuring instrument; and (d) the measuring tool (1) is part of a data measuring instrument.
According to the present invention, the received data, which are contained in each ATM cell and come from the original, continuous, synchronous digital data string, are able to be supplied at a higher rate and as bursts of data to the data measuring instrument, so that one can dispense entirely with the difficult clock recovery, since the data measuring instrument used here is suited for such a burst transmission operation. The measuring device fits on the receiving-side 19.44 Mbit/s parallel port of ATM transmission devices. It is there that ATM cells are applied. The ATM cells are composed of 53 eight-bit width data words, whose 47 useful signal words (payload) originated from originally synchronous digital data strings, whose frequency is determined by the bit rate of the originally synchronous digital data strings, and which permit the cell-by-cell reading out of the payload data. The payload data are fed consecutively and at a higher rate as burst data to a data test measuring receiver, which can ascertain the correct or corrupted receipt of the transmitting-side data without the need for a clock recovery circuit on the receiving side. Thus, measurements can be performed not only using a constant bit rate, but also with a variable bit rate of the originally synchronous digital data strings.